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19-0737; Rev 0; 2/07
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
General Description
The MAX8784 generates supply rails for the thin-film transistor (TFT) liquid-crystal display (LCD) panels in TVs and monitors. It includes a step-up regulator, a regulated positive and a negative charge-pump, three high-current operational amplifiers, and Dual ModeTM, logic-controlled, high-voltage switch control block. HVS mode automatically increases the output voltages of the boost regulator and the positive charge-pump to stress test display panels during production. The MAX8784 can operate from input voltages of 4V to 5.5V and is optimized for LCD TV panel and LCD monitor applications. The step-up DC-DC regulator provides a regulated supply voltage for TFT source drivers. The step-up regulator is a high-frequency (1.2MHz), high-efficiency, currentmode regulator. The step-up regulator has a built-in 110m (typ) power MOSFET. The high-switching frequency allows the use of ultra-small inductors and ceramic capacitors. The current-mode architecture provides fast transient response and easy compensation. The step-up regulator features output undervoltage protection, soft-start, internal current limit, and adjustable output voltage by an external resistive divider. The three operational amplifiers drive the LCD backplane and the gamma-correction-divider string. Each operational amplifier has a fast slew rate (45V/s), a wide bandwidth (20MHz), and a high-output short-circuit current (200mA). Each op amp has rail-to-rail input and rail-to-rail output operation. The positive charge-pump regulator and the negative charge-pump regulator provide regulated supply voltages for the TFT gate drivers. The positive charge pump is a two-stage charge pump, which requires no external diodes. The output voltages of both charge pumps are resistor adjustable. The logic-controlled high-voltage switch allows the manipulation of the positive TFT gate-driver supply. The MAX8784 is available in a small (5mm x 5mm), lowprofile (0.8mm), 40-pin thin QFN package and operates over the -40C to +85C temperature range.
Features
o Step-Up Regulator Supply for LCD Panel Source Driver Fast Transient Response to Pulsed Load Built-In 18V, 4A, 0.11 n-Channel Power MOSFET with Lossless Current Sensing Cycle-by-Cycle Current-Limit Comparator 90% Efficiency (5V In to 15V Out) 1.2MHz Switching Frequency o Three High-Current 19V Operational Amplifiers 180mA Output Short-Circuit Current 45V/s Slew Rate 20MHz Bandwidth Rail-to-Rail Input and Output Operation o Regulated Charge-Pump Tripler with Integrated Diodes for TFT Gate-On Supply o Regulated Charge Pump for TFT Gate-Off Supply o Built-In Sequencing Internal Digital Soft-Start 36V Gate-On Switch Startup Timing Capacitors for AVDD and GON o Undervoltage and Thermal Protection o 4V to 5.5V Input Operating Range
MAX8784
Simplified Operating Circuit
VIN STEP-UP OUTPUT
VCC POS1 TO VCOM STEP-UP OUTPUT NEG1 OUT1 POS2 NEG2 OUT2 POS3 OUT3 HVS REF AGND FBN
LX PGND
FB COMP
TO VCOM
TO VCOM
RSET GDEL ADEL
VIN
MAX8784
CTL SHDN GON DRN TCON ON/OFF VGON
Applications
LCD TVs and LCD Monitors
Ordering Information
PART MAX8784ETL+ TEMP RANGE -40C to +85C PINPACKAGE 40 Thin QFN 5mm x 5mm PKG CODE T4055-1
VGOFF DRVN PGND
POUT
FBP SUP C1N C1P C2N C2P
STEP-UP OUTPUT
+Denotes a lead-free package.
STEP-UP OUTPUT
Dual Mode is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
ABSOLUTE MAXIMUM RATINGS
VCC, CTL, HVS, SHDN, ADEL, GDEL to AGND ....-0.3V to +7.5V REF, COMP, FB, FBN, FBP to AGND .........-0.3V to (VCC + 0.3V) POS1, NEG1, POS2, NEG2, POS3, OUT1, OUT2, OUT3 to AGND .......................................-0.3V to (VSUP + 0.3) PGND, BGND to AGND.........................................-0.3V to +0.3V LX, RSET to PGND .................................................-0.3V to +22V SUP to AGND .........................................................-0.3V to +22V DRVN to AGND.........................................-0.3V to (VSUP + 0.3V) C1N, C2N to AGND ..................................-0.3V to (VSUP + 0.3V) C1P to AGND .........................................................-0.3V to +30V POUT to C2P, C1P to C2P......................................-0.3V to +22V C2P, POUT to AGND..............................................-0.3V to +40V GON, DRN to AGND ..............................................-0.3V to +40V DRN to GON............................................................-30V to +30V REF Short Circuit to AGND.........................................Continuous RMS VCC Current ................................................................50mA RMS DRVN Current...........................................................400mA LX, PGND RMS Current Rating.............................................2.4A Continuous Power Dissipation (TA = +70C) 40-Pin TQFN (derate 35.7mW/C above +70C) .......2857mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER VCC Input Supply Range VCC Undervoltage Lockout Threshold VCC rising, typical hysteresis = 50mV VFB = 1.3V, not switching VCC Quiescent Current VFB = 1.1V, switching, no load, VSUP disconnected, VFBP = VCC, VFBN = 0V SHDN = GND SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Current REFERENCE REF Output Voltage REF Load Regulation REF Sink Current REF Undervoltage Lockout Threshold OSCILLATOR and TIMING Frequency Oscillator Maximum Duty Cycle Duration to Trigger Fault Condition ADEL, GDEL Capacitor Charge Current ADEL, GDEL Turn-On Threshold STEP-UP REGULATOR FB Regulation Voltage FB Fault-Trip Level FB Load Regulation FB Line Regulation FB Input Bias Current FB = COMP, CCOMP = 1nF FB = COMP, CCOMP = 1nF, +25C to +85C Falling edge 0 < ILOAD < full VCC = 4.5V to 5.5V VFB = 1.25V 1.235 1.238 0.96 1.246 1.246 1.00 -1 0.25 100 200 1.256 1.256 1.04 V V % %/V nA 1000 87 47 4 1200 90 55 5 1.25 1400 93 65 6 1.32 kHz % ms A V No external load 0 < ILOAD < 50A In regulation Rising edge, typical hysteresis = 200mV 10 1.0 1.15 1.238 1.250 1.262 10 V mV A V 1.8 -1 +1 CONDITIONS MIN 4.0 2.4 2.6 1.0 4 6 0.05 0.8 V V A mA TYP MAX 5.5 2.8 UNITS V V
2
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER FB Transconductance LX Current Limit LX On-Resistance Current-Sense Transresistance Soft-Start Period VSUP Input Supply Range VSUP Overvoltage Charge-Pump Inhibit FBP Regulation Voltage FBP Line Regulation Error FBP Input Bias Current POUT Output-Voltage Range POUT Fixed Output Voltage POUT Output Current Limit C1N, C2N High-Side On-Resistance C1N, C2N Low-Side On-Resistance C1P Switch On-Resistance C2P Switch On-Resistance POUT Switch On-Resistance FBP Fault-Trip Level Falling edge 0.96 1.00 3 0.985 -50 0.1 10 6 Rising edge 450 3 0.8 1.8 CTL = 0V or VCC -1 200 200 VGDEL = 1.5V, CTL = VCC VPOUT - VGON > 5V VGDEL = 1.5V, CTL = 0V VGON - VDRN > 5V VGDEL = 1.0V 35 100 180 60 10 20 +1 1.00 1.015 +50 Positive Charge-Pump Soft-Start Period 7-bit voltage ramp NEGATIVE CHARGE-PUMP REGULATOR FBN Regulation Voltage FBN Input Bias Current FBN Line Regulation Error DRVN PCH On-Resistance DRVN NCH On-Resistance FBN Fault-Trip Level Negative Charge-Pump Soft-Start Period 7-bit voltage ramp POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES CTL Input-Low Voltage CTL Input-High Voltage CTL Input Current CTL-to-GON Rising Propagation Delay CTL-to-GON Falling Propagation Delay GON-to-POUT Switch On-Resistance GON-to-POUT Switch Saturation Current GON-to-DRN Switch On-Resistance GON-to-DRN Switch Saturation Current GON-to-PGND Switch On-Resistance V V A ns ns mA mA k VREF - VFBN VFBN = 250mV VSUP = 11V to 19V, VGOFF = -9V, IVGOFF = -20mA V nA %/V mV ms VSUP = 10V ~ 19V, VPOUT = 28V VFBP = 1.5V IVGON = 0mA HVS = VCC, IPOUT = 0mA Not in dropout, VSUP = 9V, VPOUT = 24V 29.1 20 30 50 9.0 6.0 15.0 10.0 10.0 1.04 -100 VSUP = rising, typical hysteresis = 200mV 7-bit current ramp 6 20 1.225 21 1.25 0.1 +100 36 30.9 POSITIVE CHARGE-PUMP REGULATOR 19 22 1.275 V V V %/V nA V V mA V ms CONDITIONS ICOMP = 2.5A, FB = COMP VFB = 1.1V, duty cycle = 75% ILX = 1.0A 0.10 MIN 75 3.5 TYP 160 4.0 0.10 0.20 3 MAX 280 4.6 0.19 0.26 UNITS S A V/A ms
MAX8784
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3
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER OPERATIONAL AMPLIFIERS SUP Supply Range SUP Overvoltage Fault Threshold SUP Supply Current Input Offset Voltage Input Bias Current Input Common-Mode Voltage Range Input Common-Mode Rejection Ratio 1V < VNEGx, VPOSx < (VSUP - 1) IOUTx = 1mA Output Voltage-Swing High IOUTx = 25mA Output Voltage-Swing Low Large-Signal Voltage Gain Slew Rate -3dB Bandwidth Short-Circuit Current HVS FUNCTION HVS Input-Low Voltage HVS Input-High Voltage HVS Input Pulldown Resistance RSET Output On-Resistance RSET Output Leakage HVS = VCC HVS = AGND 1.8 5 10 5 50 20 1 0.8 V V k A IOUTx = -1mA IOUTx = -25mA VOUTx = 1V to VSUP - 1V CLOAD = 20pF CLOAD = 20pF Short to VSUP / 2, sourcing Short to VSUP / 2, sinking 80 45 20 140 220 VSUP 50 VSUP 300 50 300 (Note 1) Buffer configuration, VPOSx = VSUP / 2, no load VNEGx, VPOSx = VSUP / 2, VNEGx, VPOSx = VSUP / 2 -1 0 80 6 19.1 20 11 19 21.0 15 12 +1 VSUP V V mA mV A V dB CONDITIONS MIN TYP MAX UNITS
mV
mV dB V/s MHz mA
ELECTRICAL CHARACTERISTICS
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER VCC Input Supply Range VCC Undervoltage Lockout Threshold VCC Quiescent Current SHDN Input-Low Voltage SHDN Input-High Voltage 1.8 VCC rising, typical hysteresis = 50mV VFB = 1.1V, switching, no load, AVDD isolated from SUP, VFBP = VCC, VFBN = 0V SHDN = GND CONDITIONS MIN 4.0 2.4 TYP MAX 5.5 2.8 6 0.05 0.8 V V UNITS V V mA
4
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER REFERENCE REF Output Voltage REF Load Regulation REF Sink Current REF Undervoltage Lockout Threshold OSCILLATOR AND TIMING Frequency Oscillator Maximum Duty Cycle Duration-to-Trigger Fault Condition ADEL, GDEL Capacitor Charge Current ADEL, GDEL Turn-On Threshold STEP-UP REGULATOR FB Regulation Voltage FB Fault Trip Level FB Transconductance LX Current Limit LX On-Resistance Current-Sense Transresistance POSITIVE CHARGE-PUMP REGULATOR VSUP Input Supply Range VSUP Overvoltage Charge-Pump Inhibit FBP Regulation Voltage POUT Output-Voltage Range POUT Fixed-Output Voltage POUT Output-Current Limit C1N, C2N High-Side On-Resistance C1N, C2N Low-Side On-Resistance C1P Switch On-Resistance CP2 Switch On-Resistance POUT Switch On-Resistance FBP fault trip level FBN Regulation Voltage DRVN PCH On-Resistance DRVN NCH On-Resistance Falling edge VREF - VFBN 0.96 0.985 NEGATIVE CHARGE-PUMP REGULATOR 1.015 10 6 V IPOUT = 0mA HVS = VCC, IPOUT = 0mA Not in dropout, VSUP = 9V VPOUT = 24V VSUP = rising, typical hysteresis = 200mV 6 20 1.225 VSUP 29.1 20 9 6 15 10 10 1.04 19 22 1.275 36 30.9 V V nA V V mA V FB = COMP, CCOMP = 1nF Falling edge ICOMP = 2.5A, FB = COMP VFB = 1.1V, duty cycle = 75% ILX = 1.0A 0.10 1.230 0.96 75 3.0 1.262 1.04 280 5.0 0.19 0.26 V V S A V/A 950 87 47 4 1.18 1400 93 69 6 1.32 kHz % ms A V No external load 0 < ILOAD < 50A In regulation Rising edge, typical hysteresis = 200mV 10 1.15 1.232 1.262 10 V mV A V CONDITIONS MIN TYP MAX UNITS
MAX8784
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER CTL Input-Low Voltage CTL Input-High Voltage GON-to-POUT Switch On-Resistance GON-to-POUT Switch Saturation GON-to-DRN Switch On-Resistance GON-to-DRN Switch Saturation Current OPERATIONAL AMPLIFIERS SUP Supply Range SUP Overvoltage Fault Threshold SUP Supply Current Input Offset Voltage Input Common-Mode Voltage Range IOUT = 1mA Output-Voltage Swing High IOUT = 25mA Output-Voltage Swing Low HVS FUNCTION HVS Input-Low Voltage HVS Input-High Voltage HVS Input Pulldown Resistance RSET Output On-Resistance HVS = VCC 1.8 5 50 20 0.8 V V k IOUT = -1mA IOUT = -25mA VSUP 300 50 300 mV (Note 1) Buffer configuration, VPOS = VSUP / 2, no load VNEG, VPOS = VSUP / 2 0 VSUP 50 mV 6 19.1 19 21.0 15 13 VSUP V V mA mV V GDEL = 1.5V, CTL = VCC VPOUT - VGON > 5V GDEL = 1.5V, CTL = 0V VGON - VDRN > 5V 35 180 60 1.8 20 CONDITIONS MIN TYP MAX 0.8 UNITS V V mA mA
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
Note 1: Step-up regulator switching is disabled above the threshold. This fault is not latched. Note 2: -40C specs are guaranteed by design, not production tested.
6
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Typical Operating Characteristics
(Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA = +25C, unless otherwise noted.)
STEP-UP REGULATOR EFFICIENCY vs. LOAD CURRENT
MAX8784 toc01
MAX8784
STEP-UP REGULATOR LOAD REGULATION
MAX8784 toc02
VCC QUIESCENT CURRENT vs. VCC
MAX8784 toc03
95
FOSC = 1.2MHz VIN = 5.0V
1.0
5
91 EFFICIENCY (%)
0.6 AVDD ERROR (%)
4
SWITCHING
IVCC (mA)
87
0.2
3
83
-0.2
2
NOT SWITCHING
79
-0.6
1
75 0 200 400 600 800 LOAD CURRENT (mA)
-1.0 0 200 400 600 800 LOAD CURRENT (mA)
0 4.0 4.4 4.8 VCC (V) 5.2 5.6 6.0
VCC QUIESCENT CURRENT vs. TEMPERATURE
MAX8784 toc04
STEP-UP REGULATOR SOFT-START (HEAVY LOAD)
MAX8784 toc05
5
4
SWITCHING
LX
IVCC (mA)
3 ILOAD 2 NOT SWITCHING IL
1 AVDD 0 -40 -15 10 35 60 85 LX: 10V/div ILOAD: 500mA/div 10ms/div IL: 20A/div AVDD: 10V/div TEMPERATURE (C)
STEP-UP REGULATOR LOAD TRANSIENT RESPONSE
MAX8784 toc06
STEP-UP REGULATOR PULSED LOAD TRANSIENT RESPONSE
MAX8784 toc07
ILOAD
AVDD
IL IL 0A AVDD IAVDD 0A 20s/div ILOAD: 200mA/div IL: 1A/div AVDD: 100mV/div (AC-COUPLED) 10s/div AVDD : 200mV/div (AC-COUPLED) IL : 1A/div IAVDD : 1A/div IAVDD : 0.3A TO 1.3A, 2s PULSE
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA = +25C, unless otherwise noted.)
TIMER-DELAY LATCH RESPONSE TO OVERLOAD
MAX8784 toc08
SWITCHING FREQUENCY vs. VCC
MAX8784 toc09
1.5 SWITCHING FREQUENCY (MHz)
IL
1.4
LX
1.3
1.2
AVDD
1.1
1.0 10ms/div AVDD: 10V/div LX: 10V/div IL: 5A/div 4.0 4.4 4.8 5.2 5.6 6.0 VCC (V)
REFERENCE LOAD REGULATION
MAX8784 toc10
SUP SUPPLY CURRENT vs. SUP VOLTAGE
ALL OUTPUTS ENABLED
MAX8784 toc11
POSITIVE CHARGE-PUMP REGULATOR LINE REGULATION
MAX8784 toc12
1.2510
9.0
2
1.2508
8.8
OUTPUT-VOLTAGE ERROR (%)
1
ISUP (mA)
VREF (V)
1.2506
8.6
0
1.2504
8.4
1.2502
8.2
-1
1.2500 0 10 20 30 40 50 IREF (A)
8.0 10 12 14 16 18 20 VSUP (V)
-2 6 9 12 15 18 21 VSUP (V)
POSITIVE CHARGE-PUMP REGULATOR LOAD REGULATION
MAX8784 toc13
NEGATIVE CHARGE-PUMP REGULATOR LINE REGULATION
MAX8784 toc114
NEGATIVE CHARGE-PUMP REGULATOR LOAD REGULATION
MAX8784 toc15
2
2
2
1
OUTPUT-VOLTAGE ERROR (%)
OUTPUT-VOLTAGE ERROR (%)
OUTPUT VOLTAGE ERROR (%)
1
1
0
0
0
VSUP = 16.0V
-1
-1
-1 VSUP = 13.5V
-2 0
10
-2 20 30 IPOUT (mA) 40 50 60 8 10 12 14 VSUP (V) 16 18 20
-2 0 50 100 150 200 250 IVGOFF (mA)
8
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA = +25C, unless otherwise noted.) HIGH-VOLTAGE SWITCH CONTROL FUNCTION
MAX8784 toc16
MAX8784
OPERATIONAL AMPLIFIER FREQUENCY RESPONSE
MAX8784 toc17
6
CGON = 1.5nF RDRN = 1k TO AVDD 3 CTL GAIN (dB) 0 CLOAD = 15pF
-3
GON -6 CLOAD = 56pF CLOAD = 33pF 0.1 GON: 10V/div 1 10 100 FREQUENCY ( MHz)
-9 10s/div CTL: 5V/div
OPERATIONAL AMPLIFIER RAIL-TO-RAIL OPERATION
MAX8784 toc18
OPERATIONAL AMPLIFIER LOAD-TRANSIENT RESPONSE
MAX8784 toc19
VOUT1 OUT1
POS1
ILOAD 2s/div
2s/div POS1: 5V/div OUT1: 5V/div VOUT1: 200mV/div
ILOAD: 100mA/div
OPERATIONAL AMPLIFIER LARGE-SIGNAL RESPONSE
MAX8784 toc20
OPERATIONAL AMPLIFIER SMALL-SIGNAL STEP RESPONSE
MAX8784 toc21
POS1
OUT1
OUT1
POS1 100ns/div
200ns/div OUT1: 5V/div POS1: 5V/div
POS1: 50mV/div (AC-COUPLED) OUT1: 50mV/div (AC-COUPLED)
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13, 19, 20, 26 14 NAME C1N C1P BGND SUP POS1 NEG1 OUT1 OUT2 NEG2 POS2 POS3 OUT3 N.C. Negative Terminal of Flying Capacitor C1 Positive Terminal of Flying Capacitor C1 Operational Amplifier and Charge-Pump Supply Ground Operational Amplifier and Charge-Pump Supply Input. Connect SUP to AVDD. Bypass SUP to BGND with 0.1F capacitor. Operational Amplifier Noninverting Input Operational Amplifier Inverting Input Operational Amplifier Output Operational Amplifier Output Operational Amplifier Inverting Input Operational Amplifier Noninverting Input Operational Amplifier Noninverting Input Operational Amplifier Output No Connection. Not internally connected. Step-Up Regulator Delay Input. Connect a capacitor from ADEL to AGND to set the delay time. A 5A current source charges CADEL. ADEL is internally pulled to AGND by a 20 resistor in shutdown. For details, see the Power-Up Sequence section. Positive Charge-Pump Startup Delay and High-Voltage Switch Delay Input. Connect a capacitor from GDEL to AGND to set the delay time. A 5A current source charges CGDEL. GDEL is internally pulled to AGND by a 20 resistor in shutdown. For details, see the Power-Up Sequence section. High-Voltage Switch Control Input. When CTL is high, the switch between GON and POUT is turned on and the switch between GON and DRN is turned off. When CTL is low, the switch between GON and DRN is turned on and the switch between GON and POUT is turned off. For details, see the High-Voltage Switch Control section. HVS Mode Input. Connect HVS to VCC to enable HVS mode. For details, see the HVS Mode section. Negative Charge-Pump Regulator Output. Connect DRVN to the negative charge-pump flying capacitor(s). Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltage-divider between the negative output and REF. Place the resistive voltage-divider within 5mm of FBN. For details, see the Output-Voltage Selection section. Reference Output. Connect a 0.22F capacitor from REF to AGND. Analog Ground VCC Supplies the Internal Reference and Other Internal Circuitry. Connect VCC to the input supply voltage and bypass VCC to AGND with a minimum 1F ceramic capacitor. Active-Low Shutdown. When SHDN is low, the device enters its low-power shutdown mode. Power Ground Step-Up Regulator Switching Node. Connect inductor and Schottky diode to LX and minimize trace area for lowest EMI. FUNCTION
ADEL
15
GDEL
16
CTL
17 18 21 22 23 24 25 27, 28 29, 30
HVS DRVN FBN REF AGND VCC SHDN PGND LX
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Pin Description (continued)
PIN 31 32 33 34 NAME AGND RSET COMP FB Analog GND Open-Drain HVS Mode Output. For details, see the HVS Mode section. Error-Amplifier Output. Connect a series RC network from COMP to AGND for compensation. Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between the stepup regulator output and AGND. Place the resistive voltage-divider within 5mm of FB. For details, see the Output-Voltage Selection section. Internal High-Voltage Switch Common Terminal. GON common terminal between the high-side p-channel MOSFET and back-to-back p-channel MOSFET. GON is internally pulled to PGND by a 100k resistor in shutdown. High-Voltage Switch Drain. Drain of the internal low-side, back-to-back p-channel MOSFET. Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive voltage-divider between POUT and AGND. Place the resistive voltage-divider within 5mm of FBP. For details, see the OutputVoltage Selection section. Positive Charge-Pump Output and High-Voltage Switch Source Input Positive Terminal of Flying Capacitor C2 Negative Terminal of Flying Capacitor C2 FUNCTION
MAX8784
35 36 37 38 39 40
GON DRN FBP POUT C2P C2N
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
VIN = 4.5V TO 5.5V C14 10F C15 10F L1 3H D1 C12 10F C13 10F AVDD 14V, 0.75A
C1 1F VCOM AVDD VCOM R1 10k
VCC POS1 NEG1 OUT1 POS2 NEG2 OUT2
LX PGND FB COMP R9 100k C11 330pF R10 20k R11 204k
POS3 R2 10k VCOM RSET OUT3 BGND HVS REF R3 20k C2 0.22F AGND FBN DRN R4 187k VGOFF -9V, 20mA C3 10F D2 C4 1F DRVN PGND SUP C1N C5 0.1F BGND C1P C2N FBP C2P R5 20k POUT R6 428k C8 1F CTL SHDN GON GDEL
R8 82k
MAX8784
ADEL C9 0.1F TCON VIN
C10 0.01F
VGON 28V, 20mA
R7 1k AVDD
AVDD
C6 0.1F
C7 0.1F
Figure 1. Typical Operating Circuit
Typical Operating Circuit
The typical operating circuit (Figure 1) of the MAX8784 is a power-supply system for TFT LCD panels in monitors and TVs. The circuit generates a +14V source-driver supply, a +28V positive gate-driver supply, and a -9V negative gate-driver supply from a 5V 10% input supply. Table 1 lists the selected components and Table 2 lists the contact information of the component suppliers.
Table 1. Component List
C1 C14, C15 C12, C13 D1 D2 L1 1F 10%, 6.3V X5R ceramic capacitor (0402) TDK C1005X5R0J105K 10F 20%, 6.3V X5R ceramic capacitors (0603) TDK C1608X5R0J106M 10F 20%, 16V X5R ceramic capacitors (1206) TDK C3216X5R1C106M 3A, 30V Schottky diode (M-flat) Toshiba CMS02 (top mark S2) 220mA, 100V dual diode (SOT23) Fairchild MMBD4148SE (top mark D4) 3.0H, 3ADC inductor Sumida CDRH6D28-3R0
Detailed Description
The MAX8784 is a multiple-output power supply designed primarily for TFT LCD panels used in monitors
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Table 2. Component Suppliers
SUPPLIER Fairchild Semiconductor Sumida TDK Toshiba PHONE 408-822-2000 847-545-6700 847-803-6100 949-455-2000
VIN
MAX8784
FAX 408-822-2102 847-545-6720 847-390-4405 949-859-3963
WEBSITE www.fairchildsemi.com www.sumida.com www.component.tdk.com www.toshiba.com/taec
POS1 NEG1 OUT1 POS2 NEG2 OUT2 POS3
SUP OSC
SHDN
LX
AVDD
BOOST
PGND FB COMP 100k 330pF
MAX8784
RSET OUT3 BGND HVS CONTROL BLOCK ADEL SEQUENCE CONTROL GDEL
HVS
VIN
VCC CTL REF AGND POUT FBN NEGATIVE REGULATOR POSITIVECHARGE PUMP C1N C1P C2N C2P REF HV SWITCH BLOCK GON DRN FROM TCON VGON
AVDD FBP
VGOFF
DRVN
BGND SUP
AVDD
Figure 2. Functional Diagram
and TVs. It has a step-up switching regulator to generate the source-driver supply, two charge-pump regulators to generate the positive and negative gate-driver supplies, and three high-current operational amplifiers. Each regulator features an adjustable output voltage and digital soft-start. The step-up regulator has cycleby-cycle current limiting and uses a fixed-frequency
current-mode control architecture with fast transient response and excellent line regulation. The MAX8784 features a high-voltage switch-control block, a very stable reference output, well-defined power-up and power-down sequences, and thermaloverload protection. Figure 2 shows the MAX8784 functional block diagram.
13
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
Step-Up Regulator
The step-up regulator employs a current-mode, fixedfrequency PWM architecture to maximize loop bandwidth and to provide fast-transient response to pulsed loads typical of TFT LCD panel source drivers. The integrated MOSFET and the built-in digital soft-start function reduce the number of external components required to control inrush currents. The output voltage can be set from VIN to 19V with an external resistive voltage-divider. The regulator controls the output voltage and output power by modulating the duty cycle (D) of the internal power MOSFET in each switching cycle. The duty cycle of the MOSFET is approximated by: V -V D AVDD IN VAVDD where VAVDD is the output voltage of the step-up regulator.
OSCILLATOR CLOCK LX LOGIC AND DRIVER CURRENT-LIMIT COMPARATOR SOFTSTART SS SLOPE COMP PWM COMPARATOR CURRENT SENSE PGND
ILIMIT
PWM Control Block Figure 3 is the block diagram of the step-up regulator controller. On the rising edge of the internal oscillator clock, the controller sets a flip-flop, turning on the nchannel MOSFET, which applies the input voltage across the inductor. The current through the inductor ramps up linearly. The transconductance error amplifier compares the FB voltage with the reference voltage. The error amplifier changes the COMP voltage by charging or discharging the COMP capacitor. The COMP voltage is compared with a ramp, which is the sum of the current-sense signal and a slope compensation signal. Once the ramp signal exceeds the COMP voltage, the controller resets the flip-flop and turns off the MOSFET. Since the inductor current is continuous, a transverse potential develops across the inductor that turns on the Schottky diode (D1 in Figure 1). The voltage across the inductor then becomes the difference between the output voltage and the input voltage. This discharge condition forces the current through the inductor to ramp down, transferring the energy stored in the magnetic field to the output capacitor and the load. The MOSFET remains off for the rest of the clock cycle.
TO FAULT LOGIC
1.0V UNDERVOLTAGE COMPARATOR
ERROR AMP FB 1.25V COMP
FREQ
Figure 3. Step-Up Regulator PWM Control Block Diagram
Soft-Start and Fault Protection The step-up regulator achieves soft-start by linearly ramping up its internal current limit. The soft-start terminates when the output reaches regulation or the full current limit has been reached. The current limit rises from zero to the full current limit in approximately 3ms. The soft-start feature effectively limits the inrush current during startup (see the Step-Up Regulator Soft-Start waveforms in the Typical Operating Characteristics). The MAX8784 monitors FB for undervoltage conditions. If the voltage is continuously below 80% of the nominal regulation point for approximately 55ms, the MAX8784 sets the fault latch, shutting down all outputs except the reference and the operational amplifier.
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Positive Charge-Pump Regulator
The positive charge-pump regulator is typically used to generate the positive supply rail for the TFT LCD gate driver ICs. The positive charge pump is a two-stage charge pump with external pump and reservoir capacitors. The output voltage is set with an external resistive voltage-divider from its output to GND with the midpoint connected to FBP. The charge pump includes internal switches with drivers to control the power transfer. Figure 4 shows the block diagram of the positive charge pump. The controller regulates the positive charge-pump output voltage such that VFBP = VREF. If VFBP goes below the reference, P1 and P3 are turned on when the rising edge of the oscillator arrives, while the drivers pull C1N to GND and C2N to SUP. The first stage flying capacitor C6
SUP O1
O2 GND
P1 01
C1N C6 C1P
O2
P2
O1 C2P C7 C2N O1 CONTROLLER O2
P3 POUT C8 LCD DISABLE COMPARATOR
(Figure 4) is charged by the charge-pump supply input and the second stage flying capacitor C7 is discharged into the reservoir capacitor C8. After a fixed period, P2 is turned on and P1 and P3 are turned off while C1N is pulled to SUP and C2N is pulled to GND. C7 is charged by C6 in preparation for the next pump cycle. The MAX8784 implements a digital variable-resistance algorithm to control the current delivered to the output. The algorithm sets the on-resistance of the positive charge-pump drivers according to the load current. The on-resistance of the drivers is set by counting the number of charging pulses in the previous 12 oscillator cycles. As the number of charging pulses in the previous 12 oscillator cycles increases, the on-resistance of the switch is reduced. The number of charging pulses in the previous 12 oscillator cycles is a measure of the load current. The period of C1N and C2N switching is 1.66s. The positive charge-pump regulator's startup can be delayed by connecting an external capacitor from GDEL to GND. An internal constant-current source begins charging the GDEL capacitor when the negative charge pump reaches regulation. When the GDEL voltage exceeds VREF, the positive charge-pump regulator is enabled. Each time it is enabled, the positive chargepump regulator goes through a soft-start routine by ramping up its internal reference voltage from 0 to VREF in 128 steps. The soft-start period is 3ms (typ) and FBP fault detection is disabled during this period. The softstart feature effectively limits the inrush current during startup. The MAX8784 monitors the FBP and SUP voltage to detect fault conditions. If VFBP is continuously below 80% of its nominal regulation point for approximately 55ms, the MAX8784 sets a fault latch, shutting down all outputs except the reference and operational amplifiers. If SUP exceeds the SUP overvoltage faut threshold (20V, typ), LX switching is inhibited until SUP decreases. Further, If SUP exceeds its overvoltage charge-pump inhibit level (21V, typ), positive charge-pump switching is inhibited until SUP decreases to prevent damage to the charge pump.
MAX8784
DISABLE ERROR AMPLIFIER
1.1*REF FBP REF
Figure 4. Positive Charge-Pump Regulator Control Block Diagram
______________________________________________________________________________________
15
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
Negative Charge-Pump Regulator
The negative charge-pump regulator (see Figure 5) generates the negative supply rail for the TFT LCD gate driver ICs. The output voltage is set with an external resistive voltage-divider from its output to REF with the midpoint connected to FBN. The number of chargepump stages and the setting of the feedback divider determine the output voltage of the negative chargepump regulator. The charge-pump controller includes a high-side p-channel MOSFET (P4) and a low-side nchannel MOSFET (N4) to control the power transfer as shown in Figure 7. The error comparator compares the feedback signal (FBN) with a 250mV internal reference. If the feedback signal is above the reference, the charge-pump regulator turns on N4 and turns off P4 when the rising edge of the oscillator clock arrives, level shifting C(NEG) in parallel with the reservoir capacitor COUT(NEG). If the voltage across COUT(NEG) minus a diode drop (VNEG VDIODE) is higher than the level-shifted flying capacitor voltage (-V C(NEG) ), charge flow from C OUT(NEG) to C(NEG) until the diode D2-B turns off. The falling edge of the oscillator clock turns off N4 and turns on P4, allowing VSUP to charge up flying capacitor C(NEG) through diode D2-A. If the feedback signal is below the reference when the rising edge of the oscillator comes, the regulator ignores this clock edge and keeps P4 on and N4 off. The negative charge-pump regulator is enabled when the step-up regulator reaches regulation. Each time it is enabled, the negative charge-pump regulator goes through a soft-start routine by ramping down its internal reference voltage from 1.25V to 250mV in 128 steps. The soft-start period is 3ms (typ) and FBN fault detection is disabled during this period. The soft-start feature effectively limits the inrush current during startup. The MAX8784 monitors FBN voltage for undervoltage conditions. If V FBN is continuously above 450mV for approximately 55ms, the MAX8784 sets a fault latch, shutting down all outputs except the reference and the operational amplifiers.
High-Voltage Switch Control
The MAX8784's high-voltage switch control block (Figure 6) consists of three high-voltage p-channel MOSFETs: Q1, between POUT and GON, Q2 and Q3 between GON and DRN. Q2 and Q3 are arranged back-to-back so that GON can be either above or below DRN. The switch control block is enabled when VGDEL goes above VREF.
VCC
SWITCH CONTROL
5A
GDEL Q4
ERROR COMPARATOR 0.25V
FAULT SHDN FBN SOFT-START DONE
POUT
SUP
Q1 VREF GON
P4 OSC DRVN C
A
Q2
D2 B
100k
N4 VGOFF GND1 COUT
CTL Q5 Q3 DRN
FBN
REF
Figure 5. Negative Charge-Pump Regulator Block Diagram
16
Figure 6. High-Voltage Switch Control Block Diagram
______________________________________________________________________________________
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
When CTL is logic high, Q1 turns on and Q2 and Q3 turn off, connecting GON to POUT. When CTL is logic low, Q1 turns off and Q2 and Q3 turn on, connecting GON to DRN. GON can be discharged through a resistor connected between DRN and GND. The switch control block is enabled when GDEL is charged to VREF. GDEL is charged by a 5A current after the negative charge pump reaches regulation. The switch control block is disabled during fault mode and during shutdown. When the switch control block is disabled, GON is pulled to PGND with an internal 100k resistor.
Reference Voltage
The reference voltage is nominally 1.246V, and can source at least 50A (see the Typical Operating Characteristics). VCC is the input of the internal reference block. Bypass REF with a 0.22F ceramic capacitor connected between REF and GND.
MAX8784
Power-Up Sequence
The MAX8784 operational amplifier and internal reference are enabled when VCC exceeds its UVLO threshold. A 5A current charges ADEL after the internal reference reaches regulation. The step-up regulator starts the soft-start sequence after ADEL is charged to VREF. The FB fault-detection circuit is enabled and the negative charge-pump regulator starts up after the step-up regulator reaches regulation. The FBN faultdetection circuit is enabled and a 5A current charges GDEL after the negative charge pump reaches regulation. The positive charge pump starts its soft-start sequence after GDEL is charged to 1.25V (typ). The FBP fault-detection circuit is enabled after the positivecharge pump reaches regulation.
Operational Amplifier
The MAX8784 has three operational amplifiers that are typically used to drive the LCD backplane (VCOM) or the gamma-correction divider string. Each operational amplifier features 140mA/220mA (source/sink) output short-circuit current, 45V/s slew rate, and 20MHz bandwidth. While the op amp is a rail-to-rail input and output design, its accuracy is significantly degraded for input voltages within 1V of its supply rails (SUP, BGND).
Short-Circuit Current Limit The operational amplifier limits short-circuit current to approximately 140mA if the output is shorted to AGND and to approximately -220mA if the output is shorted to AVDD. If the short-circuit condition persists, the junction temperature of the IC rises until it reaches the thermal-shutdown threshold (+160C typ). Once the junction temperature reaches the thermal-shutdown threshold, an internal thermal sensor immediately sets the thermal-fault latch, shutting off the main step-up regulator, the charge pumps, the high-voltage switch control block, and the operational amplifier. Those portions of the device remain inactive until the input voltage is cycled. Driving Pure Capacitive Loads The operational amplifier is typically used to drive the LCD backplane (VCOM). The LCD backplane consists of a distributed series capacitance and resistance, a load that can be easily driven by the operational amplifier. However, if the operational amplifier is used in an application with a pure capacitive load, steps must be taken to ensure stable operation.
As the operational amplifier's capacitive load increases, the amplifier's bandwidth decreases and gain peaking increases. A 5 to 50 small resistor placed between VCOM and the capacitive load reduces peaking, but also reduces the gain. An alternative method of reducing peaking is to place a series RC network (snubber) in parallel with the capacitive load. The RC network does not continuously load the output or reduce the gain.
Power-Down Control
The MAX8784 disables the step-up regulator, positive charge-pump regulator, negative charge-pump regulator, and high-voltage switch control block when SHDN is logic low. The operational amplifier depends only upon the supply voltage at SUP.
Fault Protection
During steady-state operation, if any output of the three regulators (step-up regulator, positive charge-pump regulator, and negative charge-pump regulator) is not above its respective fault-detection threshold, the MAX8784 activates an internal fault timer. If any condition or a combination of conditions indicates a continuous fault for the fault-timer duration (55ms typ), the MAX8784 sets the fault latch. The MAX8784 shuts down all the outputs except the reference and operational amplifiers after the fault latch is set. Toggle SHDN or cycle the input voltage to clear the fault latch and restart the IC.
Thermal-Overload Protection
The thermal-overload protection prevents excessive power dissipation from overheating the MAX8784. When the junction temperature exceeds TJ = +160C (typ), a thermal sensor immediately sets its fault latch, which shuts down all the outputs. After the device cools down, input voltage has to be recycled to restart. The thermal-overload protection protects the controller in the event of fault conditions. For continuous operation, do not exceed the absolute junction temperature rating of TJ = +150C.
17
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
HVS Mode
HVS mode is designed as a special operating mode for end-of-line panel testing. In HVS mode, higher than normal voltages are forced to the power-supply outputs to expose faults in the LCD panel. HVS pin is forced logic high to enable HVS mode. In HVS mode operation, FBP is ignored and the positive charge-pump regulates to a fixed-output voltage of 30V. To raise the step-up regulator output voltage in HVS operation, the open-drain RSET pin is pulled to GND. In Figure 1, resistor R8 becomes parallel to R10, which reduces the feedback resistance during HVS operation. This special feature allows the customer to select a resistor that sets an appropriate HVS voltage according to the panel requirements. The negative charge pump operates normally. Figure 7 shows the typical application circuit in HVS mode.
3H VIN = 5V 10F 10F 10F 10F
AVDD 17V, 0.65A
VCC 1F POS1 VCOM AVDD NEG1 OUT1 POS2 NEG2 OUT2 POS3 VCOM 10k
LX PGND 205k
FB COMP 100k 330pF 20k
10k VCOM
82k OUT3 RSET GDEL VIN HVS RSET = LOW
MAX8784
ADEL 0.1F
0.01F
REF 0.22F 11k AGND FBN 102k VGOFF -9V, 20mA 10F PGND SUP C1N C1P C2N FBP C2P C4 1F DRVN 432k FBP IGNORED 20k AVDD CTL SHDN GON DRN POUT VPOUT = 30V 1F FROM TCON FROM SYSTEM VGON 30V, 20mA
AVDD
0.1F 0.1F
0.1F
Figure 7. HVS Mode Operation
18
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Design Procedure
Step-Up Regulator
Inductor Selection The inductance value, peak-current rating, and series resistance are factors to consider when selecting the inductor. These factors influence the converter's efficiency, maximum output-load capability, transient response time, and output voltage ripple. Physical size and cost are also important factors to be considered. The maximum output current, input voltage, output voltage, and switching frequency determine the inductor value. Very high-inductance values minimize the current ripple and therefore reduce the peak current, which decreases core losses in the inductor and I2R losses in the entire power path. However, large inductor values also require more energy storage and more turns of wire, which increase physical size and can increase I2R losses in the inductor. Low-inductance values decrease the physical size but increase the current ripple and peak current. Finding the best inductor involves choosing the best compromise between circuit efficiency, inductor size, and cost. The equations used here include a constant LIR, which is the ratio of the inductor peak-to-peak ripple current to the average DC inductor at the full-load current. The best trade-off between inductor size and circuit efficiency for step-up regulators generally has an LIR between 0.3 to 0.5. However, depending on the AC characteristics of the inductor core material and ratio of inductor resistance to the other power-path resistances, the best LIR can shift up or down. If the inductor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. If the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. If extremely thin high-resistance inductors are used, as is common for LCD applications, the best LIR can increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficiency improvements in typical operating regions. Calculate the approximate inductor value using the typical input voltage (VIN), the maximum output current (IAVDD(MAX)), the expected efficiency (TYP) taken from an appropriate curve in the Typical Operating Characteristics, and an estimate of LIR based on the above discussion:
2 VIN VAVDD - VIN TYP LI = VAVDD IAVDD(MAX) x fSW LIR ______________________________________________________________________________________ 19
Choose an available inductor value from an appropriate inductor family. Calculate the maximum DC input current at the minimum input voltage VIN(MIN) using conservation of energy and the expected efficiency at that operating point (MIN) taken from an appropriate curve in the Typical Operating Characteristics: IIN(DCMAX) = , IAVDD(MAX) x VAVDD VIN(MIN) x MIN
MAX8784
Calculate the ripple current at that operating point and the peak current required for the inductor: ILI _ RIPPLE = VIN(MIN) x (VAVDD - VIN(MIN) ) LI x VAVDD x fSW
IAVDD _ PEAK = IIN(DCMAX) + ,
ILI _ RIPPLE 2
The inductor's saturation current rating and the MAX8784's LX current limit should exceed ILI_PEAK and the inductor's DC current rating should exceed IIN(DC,MAX). For good efficiency, choose an inductor with less than 0.1 series resistance. Considering the typical operating circuit in Figure 1, the maximum load current (IAVDD(MAX)), with charge-pump loads, is 820mA with a 14V output and a typical input voltage of 5V. Choosing an LIR of 0.35 and estimating efficiency of 85% at this operating point: 14V - 5V 5V 0.85 LI = 3.0H 14V 0.82A x 1.2MHz 0.35 Using the circuit's minimum input voltage (4.5V) and estimating efficiency of 85% at that operating point: IIN(DCMAX) = , 0.82A x 14V 3.00A 4.5V x 0.85
2
The ripple current and the peak current are: ILI _ RIPPLE = 4.5V x (14V - 4.5V ) 0.69A
3.0H x 14V x 1.2MHz
ILI _ PEAK = 3.0A +
0.69A 3.35A 2
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
Output-Capacitor Selection The total output-voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due to the capacitor's equivalent series resistance (ESR):
VAVDD _ RIPPLE = VAVDD _ RIPPLE(C) + VAVDD _ RIPPLE(ESR)
Loop Compensation Choose RCOMP (R9 in Figure 1) to set the high-frequency integrator gain for fast transient response. Choose CCOMP (C11 in Figure 1) to set the integrator zero to maintain loop stability.
For low-ESR output capacitors, use the following equations to obtain stable performance and good transient response: RCOMP 251x VIN x VAVDD x C AVDD LI x IAVDD(MAX) VAVDD x C AVDD 10 x IAVDD(MAX) x RCOMP
VAVDD _ RIPPLE(C) and:
IAVDD VAVDD - VIN C AVDDT VAVDD x fSW
VAVDD _ RIPPLE(ESR) IAVDD _ PEAK x RESR _ AVDD where IAVDD_PEAK is the peak inductor current (see the Inductor Selection section). For ceramic capacitors, the output-voltage ripple is typically dominated by VAVDD_RIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered.
CCOMP
To further optimize transient response, vary RCOMP in 20% steps and CCOMP in 50% steps while observing transient response waveforms. If additional noise rejection is desired, add a high-frequency pole by placing a 10pF to 47pF capacitor from COMP to GND.
Input-Capacitor Selection The input capacitor reduces the current peaks drawn from the input supply and reduces noise injection into the IC. Two 10F ceramic capacitors are used in the Typical Operating Circuit (Figure 1) because of the high source impedance seen in the typical lab setups. Actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. Typically, the input capacitance can be reduced below the values used in the Typical Operating Circuit. Rectifier Diode The MAX8784's high switching frequency demands a high-speed rectifier. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. In general, a 2A Schottky diode complements the internal MOSFET well. Output-Voltage Selection The output voltage of the step-up regulator can be adjusted by connecting a resistive voltage-divider from the output (AVDD) to AGND with the center tap connected to FB1 (see Figure 1). Select R10 in the 10k to 50k range. Calculate R11 with the following equation:
V R11 = R10 x AVDD - 1 VFB where V FB is the step-up regulator's feedback set point. Place R10 and R11 close to the IC.
Charge-Pump Regulators
Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meet the output requirement. The number of negative charge-pump stages is given by:
nNEG = -VGOFF + VDROPOUT VSUP - 2 x VD
where nNEG is the number of negative charge-pump stages, VGOFF is the output of the negative chargepump regulator, V SUP is the supply voltage of the charge-pump regulators, VD is the forward voltage drop of the charge-pump diode, and V DROPOUT is the dropout margin for the regulator. Use VDROPOUT = 0.6V. The above equations are derived based on the assumption that the first stage of the negative charge pump is connected to ground. Sometimes fractional stages are more desirable for better efficiency. This can be done by connecting the first stage to VIN or another available supply. If the first-stage charge pump is powered from VIN, then the above equation becomes: nNEG = -VGOFF + VDROPOUT + VIN VSUP - 2 x VD
The MAX8784's positive charge-pump regulator is a fixed two-stage charge pump with built-in switches.
20
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Pump Capacitors Increasing the pump capacitor value (C4, C6, and C7) lowers the effective source impedance and increases the output-current capability. Increasing the capacitance indefinitely has a negligible effect on output current capability because the internal switch resistance and the diode impedance place a lower limit on the source impedance. A 0.1F ceramic capacitor works well in most low-current applications. For the negative charge pump, the flying capacitor's voltage rating must exceed the following:
VCX > n x VSUP where n is the stage number in which the flying capacitor appears. For the positive charge pump, the pump capacitor's voltage rating must exceed the following: VC6 > VSUP VC7 > 2 x VSUP Adjust the negative charge-pump regulator's output voltage by connecting a resistive voltage-divider from VGOFF to REF with the center tap connected to FBN (Figure 1). Select R3 in the 20k to 68k range. Calculate R4 with the following equation: V -V R4 = R3 x FBN GOFF VREF - VFBN where VREF - VFBN is the negative charge-pump regulator's feedback set point. Note that REF can only source up to 50A. Using a resistor less than 20k for R2 results in higher bias current than REF can supply.
MAX8784
PCB Layout Grounding
Careful PCB layout is important for proper operation. Use the following guidelines for good PCB layout: * Minimize the area of respective high-current loops by placing step-up regulator's inductor, diode, and output capacitors near its input capacitors and its LX and PGND pins. For the step-up regulator, the high-current input loop goes from the positive terminal of the input capacitor to the inductor, to the IC's LX pins, out of PGND, and to the input capacitor's negative terminal. The high-current output loop is from the positive terminal of the input capacitor to the inductor, to the output diode (D1), to the positive terminal of the output capacitors, reconnecting between the output capacitor and input capacitor ground terminals. Connect these loop components with short, wide connections. Avoid using vias in the high-current paths. If vias are unavoidable, use many vias in parallel to reduce resistance and inductance. Create a power ground island (PGND) for the stepup regulator, consisting of the input and output capacitor grounds and the PGND pin. Connect all these together with short, wide traces or a small ground plane. Create an analog ground plane (AGND) consisting of the AGND pin, all the feedback-divider ground connections, the COMP, ADEL, and GDBL capacitor ground connections, and the device's exposed backside pad. Place all feedback voltage-divider resistors as close as possible to their respective feedback pins. The divider's center trace should be kept short. Placing the resistors far away causes their FB traces to become antennas that can pick up switching noise. Care should be taken to avoid running any feedback trace near LX, DRVN, C1N, C1P, C2N, or C2P.
Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the output-voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value:
COUT _ CP ILOAD _ CP 2fOSCVRIPPLE _ CP *
where COUT_CP is the output capacitor of the charge pump, I LOAD _ CP is the load current of the charge pump, and VRIPPLE_CP is the peak-to-peak value of the output ripple.
Output-Voltage Selection Adjust the positive charge-pump regulator's output voltage by connecting a resistive voltage-divider from POUT to GND with the center tap connected to FBP (Figure 1). Select the lower resistor of divider R5 in the 10k to 30k range. Calculate upper resistor R6 with the following equation:
V R6 = R5 x POUT - 1 VFBP where VFBP is the positive charge-pump regulator's feedback set point.
*
______________________________________________________________________________________
21
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
* Place VCC pin and REF pin bypass capacitors as close as possible to the device. The ground connection of the V CC bypass capacitor should be connected directly to the AGND pin with a wide trace. Minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. Minimize the size of the LX node while keeping it wide and short. Keep the LX and charge-pump nodes away from feedback nodes (FB, FBP, and FBN) and analog ground. Use DC traces as a shield if necessary.
Pin Configuration
PGND PGND SHDN AGND N.C. VCC LX LX
TOP VIEW
*
30 29 28 27 26 25 24 23 22 21 AGND 31 RSET 32 COMP 33 FB 34 GON 35 DRN 36 FBP 37 POUT 38 C2P 39 C2N 40 1 C1N 2 C1P 3 BGND 4 SUP 5 POS1 6 NEG1 7 OUT1 8 OUT2 9 NEG2 10 POS2 20 N.C. 19 N.C. 18 DRVN 17 HVS 16 CTL
*
MAX8784
REF
FBN 15 GDEL 14 ADEL 13 N.C. 12 OUT3 11 POS3
Refer to the MAX8784 evaluation kit for an example of proper board layout.
Chip Information
TRANSISTOR COUNT: 11,424 PROCESS: BiCMOS
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Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX8784
______________________________________________________________________________________
QFN THIN.EPS
23
Step-Up Regulator, Internal Charge Pumps, Switch Control, and Operational Amplifier for TFT LCDs MAX8784
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.

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